1. Field of the Invention
The invention relates to an eFuse (electrically programmable fuse) macro, and more particularly to an eFuse macro using a serious condition for a test mode.
2. Description of the Related Art
Electrical programmable fuses (eFuses) are applied in many electronic devices. An eFuse may be programmed by blowing the eFuse after a chip is manufactured. The eFuses in VLSI silicon devices are conventionally programmed by applying a relatively large amount of power (e.g. a current with sufficient magnitude and duration) to the fuse to be programmed, so as to melt and separate the fuse body material. This changes the resistance of the eFuse from a low pre-blow resistance to a high post-blow resistance. According to the resistance of the eFuse, the state of the eFuse is sensed to determine whether the eFuse is blown or not, i.e. the eFuse is a blown fuse (programmed) or a natural fuse (un-programmed)
For a programmable device, an eFuse macro is normally configured as a chain or two-dimensional array containing at least one eFuse unit and a supporting logic circuit thereof, wherein the eFuse unit comprises one or more fuses associated with the programming and sensing circuits thereof. In general, a blown fuse may typically have a resistance greater than that of a fuse that is not blown. For example, a normal fuse that is not blown may have a resistance range from 100Ω to 1 kΩ, and a normal blown fuse may have a resistance range from 5 kΩ to 10 kΩ. However, sometimes, a blown fuse may have a resistance lower than the normal blown fuse due to process variation, programmed power or other factors, i.e. the resistance of the blown fuse is abnormal. When the blown fuse with abnormal resistance is sensed, it is very difficult to distinguish the state of the blown fuse, i.e. the blown fuse with abnormal resistance may be taken as a fuse that is not blown, thereby worsening defective parts per million (DPPM).
FIG. 1A shows a schematic of a fuse unit 100 with a reference resistor 120. The fuse unit 100 comprises a fuse 110, a reference resistor 120 and a sensing unit 130, wherein the fuse 110 is coupled between the sensing unit 130 and a ground GND and the reference resistor 120 is coupled between the sensing unit 130 and the ground GND. The sensing unit 130 senses the resistances of the fuse 110 and the reference resistor 120 to determine whether the fuse 110 is blown or not, i.e. the fuse 110 is a blown fuse or a natural fuse, wherein the resistance of the reference resistor 120 is between the resistances of the blown fuse and the natural fuse. However, the determination of the sensing unit 130 may be wrong, if the resistance of the fuse 110 is very close to the resistance of the reference resistor 120 due to process variations or other factors, i.e. the fuse 110 is a blown fuse with marginal fail resistance which is an abnormal blown fuse has a resistance similar to the reference resistor.
FIG. 1B shows a schematic of a fuse unit 200 without a reference resistor. The fuse unit 200 comprises a fuse 210, an NMOS 220, a PMOS 230 and a buffer 240. The fuse 210 is coupled between the ground GND and the NMOS 220, and the NMOS 220 is coupled between the fuse 210 and a node N1. The PMOS 230 has a drain coupled to a voltage VCC and a source coupled to the node N1 between the NMOS 220 and the buffer 240, wherein the PMOS 230 with a longer length may function as a resistor. The NMOS 220 may function as a switch controlled by a signal RD, wherein the signal RD is present when the state of the fuse 210 is to be read or sense. When the NMOS 220 is turned on, the buffer 240 receives a voltage from the node N1 and then provides an output signal Sout indicating whether the fuse 210 is blown or not by determining whether the voltage from the node N1 exceeds a trigger point of the buffer 240. However, once the resistance of the fuse 210 being abnormal due to process variations, the voltage of the node N1 may influence the determination of the buffer 240, thus a wrong output signal Sout may be obtained.